Re: gEDA-user: VeriWell now on SourceForge

[Shawn Tan <shawn.tan@xxxxxxxxx>]

> What we need isn't a Verilog simulator, what we need is a VHDL
> simulator, and maybe even some means of using both Verilog and VHDL
> together in a single design.  It has always baffled me how Verilog
> simulators seem to be literally everywhere, but if OpenCores is any
> indication, ALL the truely interesting designs are VHDL.

*ALL* ?? interesting?? might need to do a poll on that.. when i last checked, 
i think that most of the designs on opencores are in verilog.. Anyway, from 
my experience, VHDL is usually taught in schools while Verilog is more widely 
used in industry.. Don't know what that is but it is.. 

cheers..

-- 
with metta,
Shawn Tan