Re: gEDA-user: VeriWell now on SourceForge

[Karel Kulhavy <clock@xxxxxxxxxxxxx>]

On Mon, Sep 26, 2005 at 11:17:10PM -0700, Samuel A. Falvo II wrote:
> On 9/26/05, Evan Lavelle <eml-geda@xxxxxxxxxxx> wrote:
> > https://sourceforge.net/projects/veriwell/
> > http://www.deepchip.com/items/0447-11.html
> 
> What we need isn't a Verilog simulator, what we need is a VHDL
> simulator, and maybe even some means of using both Verilog and VHDL
> together in a single design.  It has always baffled me how Verilog
> simulators seem to be literally everywhere, but if OpenCores is any
> indication, ALL the truely interesting designs are VHDL.

What is better, Verilog or VHDL?

I have seen VHDL and Verilog and got a feeling that Verilog is like C,
while VHDL is like Pascal, which made me immediately puke upon VHDL.

CL<