Re: gEDA-user: Icarus verilog Synthesis

[Philipp Klaus Krause <pkk@xxxxxxx>]

Am 04.09.2010 06:19, schrieb Ronald Mathias:
> 
> 
>    I transform the Verilog code containing behavioral statements into
>    verilog code that contains only gate level instantiations. This is
>    passed as input to ABC Logic synthesis tool. Finally the
>    output generated by ABC is passed to Versatile Place and Route(VPR)
>    program which generates the bitstream.


You don't have to go down to gate level: Simple verilog, (e.g. still
allowed to use '+', '-', but not '*', etc) can be read by vl2mv, you can
the use vis to flatten the resulting blif-mv into blif, which can be
read by abc.
This is the way I currently do synthesis (for a simulated asic, directly
writing the simple verilog vl2mv understands; the resulting gate level
verilog is then simulated in Icarus to get timing).

Philipp


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