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Re: gEDA-user: Color silk layers in pcb

On Fri, 2010-09-03 at 11:53 +0200, Pawel Kusmierski wrote:

As a kludge, call your layer by one of the magic names "outline" or
"route" and it will be ignored by the DRC, and treated as non-copper.

Regards,

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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