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Re: gEDA-user: Color silk layers in pcb

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Subject: Re: gEDA-user: Color silk layers in pcb
From: Pawel Kusmierski <drab.odr@xxxxxxxxx>
Date: Sat, 4 Sep 2010 22:56:58 +0200
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On Sat, Sep 4, 2010 at 1:11 PM, Peter Clifton <pcjc2@xxxxxxxxx> wrote:
> As a kludge, call your layer by one of the magic names "outline" or
> "route" and it will be ignored by the DRC, and treated as non-copper.
>

Peter, thanks for the tip.
I may be doing something wrong, but even following the tips at
http://www.geda.seul.org/wiki/geda:pcb_tips#how_do_i_make_a_board_outline_to_go_with_my_gerbers_to_the_board_maker
the outline layer still connects my vias together.

Kind regards,
-- 
Pawel Kusmierski

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