Re: gEDA-user: Color silk layers in pcb

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Sat, 2010-09-04 at 22:56 +0200, Pawel Kusmierski wrote:
> On Sat, Sep 4, 2010 at 1:11 PM, Peter Clifton <pcjc2@xxxxxxxxx> wrote:
> > As a kludge, call your layer by one of the magic names "outline" or
> > "route" and it will be ignored by the DRC, and treated as non-copper.
> >
> 
> Peter, thanks for the tip.
> I may be doing something wrong, but even following the tips at
> http://www.geda.seul.org/wiki/geda:pcb_tips#how_do_i_make_a_board_outline_to_go_with_my_gerbers_to_the_board_maker
> the outline layer still connects my vias together.


Hmm, so it does.. sorry, it appears the DRC check isn't disabled for the
"outline" layer.

What is useful is that the "outline" / "route" titled layers don't get
pads flashed on them when exporting gerbers. All other (copper) layers
get the pads on them, which would be a problem for an outline plot.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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