Re: gEDA-user: Color silk layers in pcb

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Sun, 2010-09-05 at 00:18 +0200, Levente Kovacs wrote:
> On Sat, 4 Sep 2010 11:24:38 +0000
> Ineiev <ineiev@xxxxxxxxx> wrote:
> 
> > Probably this patch may be used as a workaround.
> 
> Why don't we just push this patch to HEAD? This works just great.

One minor nit..

I'd keep the "non-copper" / "skip-drc" ideas separate. We might (at some
point) have DRC rules for non-copper layers (not that I can think of
them at the moment, perhaps apart from silk layer(s)).

Otherwise, seems good.

Best regards,

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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