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Re: gEDA-user: Color silk layers in pcb

   On Sun, Sep 5, 2010 at 2:19 PM, Peter Clifton <[1]pcjc2@xxxxxxxxx>
   wrote:

     On Sun, 2010-09-05 at 00:18 +0200, Levente Kovacs wrote:
     > On Sat, 4 Sep 2010 11:24:38 +0000
     > Ineiev <[2]ineiev@xxxxxxxxx> wrote:
     >
     > > Probably this patch may be used as a workaround.
     >
     > Why don't we just push this patch to HEAD? This works just great.
     One minor nit..
     I'd keep the "non-copper" / "skip-drc" ideas separate. We might (at
     some
     point) have DRC rules for non-copper layers (not that I can think of
     them at the moment, perhaps apart from silk layer(s)).
     Otherwise, seems good.
     Best regards,
     --
     Peter Clifton
     Electrical Engineering Division,
     Engineering Department,
     University of Cambridge,
     9, JJ Thomson Avenue,
     Cambridge
     CB3 0FA
     Tel: +44 (0)7729 980173 - (No signal in the lab!)
     Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)
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   If PCB had the concept of a part/element body outline layer (separate
   from the silk),  it could be used as a guide for part placement, not
   interfere with pads like
   the silk would, and could be checked with the DRC.  Another vote for
   general, non-copper layers I guess.
   Joe T.

References

   1. mailto:pcjc2@xxxxxxxxx
   2. mailto:ineiev@xxxxxxxxx
   3. mailto:geda-user@xxxxxxxxxxxxxx
   4. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user


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