Re: gEDA-user: Color silk layers in pcb

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Mon, 2010-09-06 at 09:30 +0200, Kovacs Levente wrote:
> On Sun, 05 Sep 2010 22:19:08 +0100
> Peter Clifton <pcjc2@xxxxxxxxx> wrote:
> 
> > I'd keep the "non-copper" / "skip-drc" ideas separate. We might (at
> > some point) have DRC rules for non-copper layers (not that I can
> > think of them at the moment, perhaps apart from silk layer(s)).
> 
> Component outline vs. keep-in component layer, etc.
> 
> However at this point where we are now, this patch would be great help.

My point was that the patch muddles the "non-copper" / "skip-drc"
concepts, and this should be fixed before the patch is applied.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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