Re: gEDA-user: Color silk layers in pcb

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Mon, 2010-09-06 at 15:32 +0200, Kai-Martin Knaak wrote:
> Peter Clifton wrote:
> 
> >> Why don't we just push this patch to HEAD? This works just great.
> > 
> > One minor nit..
> > 
> That is, the patch is rejected because of this minor nit?

I don't accept / reject patches per-se.. I was just making a comment
having read the patch. Personally I'd like to see it fixed before it is
applied.

- I don't object to the patch in principle (baring the comment I made)
- I'm not holding the patch to ransom,
    suggesting _I_ would apply it if certain changes were made.
- I'm not currently intending to apply the patch myself
    (as I've not the time to review its design implications)

Bug-fix patches are usually pretty easy to review and apply, but ones
which affect the parsing / semantics of the file format (including
various new attributes) need to be reviewed carefully, since forward
compatibility is very important.

I don't want to see PCB gathering a legacy of ill-thought out semantics
which might cause difficulties in the future (either code or file-format
wise). (Again, I've got nothing against the patch in question).

Is attribute based layer control the direction we want to take PCB in? I
personally think so - "probably" at least ;).

Are the attribute(s) suitably name-spaced / future proof?
(I just don't know).

However - as I pointed out.. confusing "non-copper" with "skip-drc" is
probably a bad idea. From my brief skim of the patch, this seemed like
it might have only been done in code comments, so is _really_ easy to
rectify.


I don't have the time to dig deeper into these questions right now, but
they are important before we end up with a legacy of attributes which do
"magic" things inside PCB. (Not that I think the proposed ones are bad).

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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