Re: gEDA-user: Color silk layers in pcb

[kai-martin knaak <kmk@xxxxxxxxxxxxxxx>]

Peter Clifton wrote:

> What is useful is that the "outline" / "route" titled layers don't 
> get pads flashed on them when exporting gerbers. All other (copper)
> layers get the pads on them, which would be a problem for an
> outline plot.

Apparently not for my preferred fab. When asked, they told me that pads 
on the outline are no problem to them. They cut the pcb at places where 
the gerber asks for copper. For some projects I needed copper at the 
very edge of the PCB. So I had to ignore the corresponding DRC errors.

Conclusion: I'd like to have the outline layer ignored by DRC, too.

---<)kaimartin(>---
-- 
Kai-Martin Knaak
Öffentlicher PGP-Schlüssel:
http://pgp.mit.edu:11371/pks/lookup?op=get&search=0x6C0B9F53



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