Re: [f-cpu] Free synthesis tool for Verilog and other links

[Ben Franchuk <bfranchuk@jetnet.ab.ca>]

Just an Illusion wrote:

> The problem with schematics is that they are in proprietary format, 
> which are incompatible between tools.
> More, synthesizer don't like them (I don't no why but when I try to give 
> them circuit like postscript, jpeg, png files... They crush :-D).

True, but I am visible person I like to see block diagrams and such.
The schematic problem is one due to lack of tools rather than a poor data
entry format.
I would also go so far as to say even the HDL's are proprietary formats
because of the minor diferences in compilers. I suspect most venders of the
tools don't want portablity but rather just have you to stick with their product.


> It seems than some peoples misunderstood what we have in a hdl code 
> (verilog or vhdl).

I want more choice than that, but since I am NOT FPGA vender or some BIG
GOVERMENT AGENCY I have no say in the matter.

> With the same language, we can describe 3 main level of abstraction of 
> the same design (or function) :
> 
> - The behavioral level, where you describe the dataflow treatment 
> without any preoccupation of register transmission, synchronism 
> implementation...
> - The structural level (named *rtl*, for Register Transfert Level), 
> where you describe one of the implementation possibility of the previous 
> behavioral model. At this level, you need define the registers, the 
> synchronism clocks...
> - The gate level (or netlist) where you made a implementation of the 
> previous levels, and describe like primary blocks interconnexion.

I can't see how the behavorial level be a major level above the RTL level?
All operations still have fully defined.  a <- b * c may look ok but what
about overflow, signed vs unsigned and other parameters.
But then too I have used a computer (PDP-8/S) that used real transistors
diodes and other components. If something breaks you fix it, not like today's
computers. I still like to stay close to the hardware level.
Note I am questioning the tools that can be used here, not how the F-CPU
is implimented. The F-CPU seems to be comeing along nicely.

-- 
Ben Franchuk - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html

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