Re: gEDA-user: CPLDs and other high-density logic chips...

[Mike Jarabek <mjarabek@xxxxxxxxx>]

On Sun, 2006-09-03 at 15:57 +1000, John Sheahan wrote:
> Samuel A. Falvo II wrote:
> > I am working on a project that, in the end, may require me to utilize
> > a CPLD just to get the thing working and cost-effective.  But I really
> > have no knowledge of how to prototype with such beasts.
> > 
> > Is there a body of resources that you folks would recommend to a
> > *total* neophyte with respect to CPLDs and FPGAs?  The farthest I've
> > gotten in Verilog was to actually get something to simulate via
> > Icarus, but actual synthesis and resynthesis is something that still
> > escapes me, unfortunately.
> 
> you probably want to choose either Xilinx or Altera for a start.
> Both make good things.
> 

Don't discount Lattice either,  they are #3, and they have a line of
FPGA devices the 'EC' family that has a programmable array that has FPGA
properties, but also has built in Flash to download the bitstream.  You
get the best of both worlds, non-volatility, and fine grained FPGA
architecture.  Some of the devices also have built in core voltage
regulators too, so all you need is 3.3V to power them.  There are some
smaller devices that have built in block ram and a goodly number of
logic elements to use for circuitry.  The program with JTAG, so all you
need is a cable.  The Official Lattice cable might set you back about
$200 if you pay full price, but you can build one with a bus buffer and
a DB-25 connector.

> once that choice is made, visit their web site for docs.
> 
> if you have code that simulates, you need to add a file mapping IO's
> to pins, a wrapper instantiating IO drivers, and you are pretty much done.
> 
> For example, if you were to pick xilinx, and with what you have 
> mentioned, you might want to drop the cpld, put a small spartan device 
> on the board, and add a configuration device for that.
> 
> your tool budget is then just a programmer for the configuration device.
> icarus and the web tools will do the rest.
> 
> > 
> > Also, what kind of capital investment am I looking at?

The tool download and use should be free for smaller devices.  I just
used Quartus II web edition to design a simple text mode VGA controller
in an Altera Cyclone II '35 device and it took up 1% of the 33,000 logic
elements!  That leave lots of other room for other bits to put in there.
These things have gotten huge, even for the free versions of the
tools. ;-)

> > 
> > My plan was to use a relatively simple CPLD for address decoding and
> > other glue logic functions, but also perhaps an FPGA for generating
> > VGA (640x480) video.
> > 
> 
> this would work - but is probably 1 device more than required.
> 1 is usually easier than 2.
> john
> 
> 
> > Thanks.
> > 
> 
> 
> 
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-- 
--------------------------------------------------
                              Mike Jarabek        
                                FPGA/ASIC Designer
  http://www.istop.com/~mjarabek                    
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