Re: [f-cpu] Conditionnal load and store, the return

["Christophe Avoinne" <christophe.avoinne@laposte.net>]

----- Original Message -----
From: "Cedric BAIL" <cedric.bail@free.fr>
To: <f-cpu@seul.org>
Sent: Wednesday, August 28, 2002 11:15 PM
Subject: Re: [f-cpu] Conditionnal load and store, the return



> The problem is that you didn't have any error in fact the test is false,
so no
> real memory access are done. So you must not reexecute the instruction and
only
> pass it even if the address is bad. It's were I see a problem, you execute
a
> handler for nothing...
>
'loadCC' : If you access memory regardless the test result, yes you will
raise an exception even for false test. Due to this design you need to delay
the exception until the test is completed and is true.
'storeCC' : You should only access memory if the test succeeds so I don't
see how an exception can be done when the test is false, since I suppose we
only store in memory if the test is true.
'lload' : no problem.
'lstore' : same thoughts than 'storeCC'.

You should really detail your explanation because I really don't see how you
planned to execute 'loadCC' and 'storeCC' and find out that kind of problem.

A+

*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/