some FPGAs can be had with a thousand pins, expensive but much less
than if we designed our own G-chip with as many pins. And we can develop
the routing algorithms, etc, without having to going to fundry.
The basic idea is that the F-CPU contains a DMA engine that transfers
data from I/O to memory and vice versa. When the chip is reset, the
engine would be preset to receive a fixed amount of data from the I/O
bus and transfer it to a fixed physical address (most likely zero)
where the F-CPU can execute it.
That, or a simpler way :
init PC=0,
which triggers cache fault, (because RESET has flushed everything)
so reads from outside memory (private memory is not mapped to address 0)
---> no need to design the DMA specificically for booting.