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Re: [f-cpu] F-CPU architecture...

Hi two,

With the advent of a new organisation (with FC0 having one specific I/O channel),
the "G chip" can be a simple FPGA. This makes it much more cost-effective and practical :

And slow?

some FPGAs can be had with a thousand pins, expensive but much less
than if we designed our own G-chip with as many pins. And we can develop
the routing algorithms, etc, without having to going to fundry.

Well, we don't need so many pins for I/O. A unidirectional 1 Gbps lane will give us throughputs of up to 100 MB/s. If we use e.g. 16 lanes in either direction (1.6 GB/s), then we need 64 pins on the F-CPU and 256 on the G-chip (differential signals assumed).

The basic idea is that the F-CPU contains a DMA engine that transfers data from I/O to memory and vice versa. When the chip is reset, the engine would be preset to receive a fixed amount of data from the I/O bus and transfer it to a fixed physical address (most likely zero) where the F-CPU can execute it.

That, or a simpler way :
init PC=0,
which triggers cache fault, (because RESET has flushed everything)
so reads from outside memory (private memory is not mapped to address 0)
---> no need to design the DMA specificically for booting.

Whether the DMA starts idle or waits for data from the I/O port is simply a matter of toggling control bits, IMHO.

Michael "Tired" Riepe <michael@xxxxxxxx>
X-Tired: Each morning I get up I die a little
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