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Re: [f-cpu] Smooth Register backup issues...

hi,

nico@seul.org wrote:
On Thu, Nov 13, 2003 at 10:47:53PM +0100, Beat Steiner wrote:

Some thoughts about SRB:

<snip>
Did anybody say "Zilog Z80"? ;)

Or ARM. That's called swadow register. The problem with SRB is :
- how do you handle nested interrupt ?
- how do you "allocate" a new CMB ?
- If saving is automatique even on very light it handler you must save all
of the register.

(see answers and old solutions in another post)


I would prefer a much lighter solution : 16 swadow registers.
light ?
here we are not speaking of an ARM-class CPU (which is "light" because it has only 16 x 32-bit registers).

first this suggestion breaks the architecture's orthogonality.
second, it adds silicon area, not only with the shadow itself, but also all the control signal
decoding and data paths.
third, i don't think it solves anything, it rather pushes the problem back to another level
where you will forget it.

If the it handler need more space it save some. If it needed nested interrupt, the
software managed it.

"show me your code".


The only adding interresting fonctionnality is to have 2 shadow register bank.


"why do bad when we can do worse ?" :-)
On dedicated ton exception normaly trap by the OS, and one for
external interrupt trap to drivers. Those you could managed crapy drivers
without crashing the all system.

you want 1 shadow per exception type/category ???
nicO

YG
/away to buy some potentiometers

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