Re: [f-cpu] Smooth Register backup issues...

[Michael Riepe <Michael.Riepe@stud.uni-hannover.de>]

Hi gang,

nico@seul.org wrote:

> [...] The problem with SRB is :
> - how do you handle nested interrupt ?
> - how do you "allocate" a new CMB ?
> - If saving is automatique even on very light it handler you must save all
> of the register.
I asked that myself a long time ago.  And didn't get an answer.

We have to distinguish between interrupts and task switches. An
(asynchronous) interrupt will suspend the running task for a while, and
then return to it. A task switch stops the current task and start a new 
one. A software interrupt (e.g. system call) is similar to a hardware 
interrupt but will run in the context of the current task (i.e. no SRB 
is performed).

When a task is created, the OS will allocate a CMB for it. When the OS
(or the CPU) switches from task A to task B, the CPU will have to save
register values to the CMB of task A and load new values from the CMB of
task B. It can do so beforehand or on an as-needed basis. With shadow
registers, it could swap register banks, trigger an SRB-SAVE for the now
invisible bank, switch CMBs and start running the new task, performing 
an SRB-RESTORE while it continues.

Hardware interrupts work similar, but they usually have no task context.
Register values of the current task will have to be saved to the task's 
CMB on entry, and restored when the interrupt service routine ends. With 
shadow registers, you can simply swap register banks - but you'll have 
to take care that a running SRB-SAVE for the shadow set (caused by a 
task switch) is finished first.

In order to make the interrupt service routine itself interruptible, you 
can allocate a CMB for it and switch CMBs manually. Or you just turn off 
interrupts until the ISR finishes (provided that the ISR is short). This 
won't work with exceptions, however, because they may nest. Maybe they 
should run inside their own task context (with a pre-allocated CMB).


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