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Re: [f-cpu] Smooth Register backup issues...

> On Thu, Nov 13, 2003 at 10:47:53PM +0100, Beat Steiner wrote:
>> Some thoughts about SRB:
>> Expensive approach: On initiation of SRB, all registers are backed
>> up to a mirror set of registers. Every register is directly connected
>> to its mirror partner (makes 64x63 connections!). Mirroring can
>> take place in one clock cycle this way (much like a snapshot backup
>> of a journaling filesystem). Writing out the backup to the RAM is
>> performed as described in the SRB section of the manual.
>> Cheap approach: The compiler shuffles up registers in a random way,
>> reducing the probability that r1 has always to be backed up and is the
>> first register used by the new context (programmers tend to use r1
>> first).
> r1...r15 hold the arguments of a function (or system call).  That is,
> at least some of them will be in use most of the time.  Well-optimized
> code should use as many registers as possible, so most other registers
> will be busy as well (and unused argument registers can be reclaimed
> and used as temporaries).
> I prefer a double-buffering approach: The "shadow" register is loaded
> from the new ("incoming") CMB, while the "foreground" register is
> saved to the old ("outgoing") CMB.  As soon as the shadow is loaded,
> register and shadow can be swapped (by flipping an address or enable
> bit).  That way, a direct connection between a register and its
> shadow counterpart is not required since you never have to transfer
> data between them.  In addition to that, it enables you to process
> interrupts very quickly -- just swap the registers on entry and exit
> of the interrupt service routine.
> Did anybody say "Zilog Z80"? ;)

Or ARM. That's called swadow register. The problem with SRB is :
- how do you handle nested interrupt ?
- how do you "allocate" a new CMB ?
- If saving is automatique even on very light it handler you must save all
of the register.

I would prefer a much lighter solution : 16 swadow registers. If the it
handler need more space it save some. If it needed nested interrupt, the
software managed it.

The only adding interresting fonctionnality is to have 2 shadow register
bank. On dedicated ton exception normaly trap by the OS, and one for
external interrupt trap to drivers. Those you could managed crapy drivers
without crashing the all system.


> --
>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
>  "All I wanna do is have a little fun before I die"
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