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Re: gEDA-user: 3 questions on a 4 layer board
At 04:33 PM 4/29/2008, you wrote:
>Dan McMahill wrote:
> > If my traces were carrying ground referenced analog signals I wouldn't
> > want the power plane being my "ground" plane.
> >
> > And yes, I've seen a real life case with some rather frustrating
> > behavior that the correct stackup totally fixed. There was a moment of
> > clarity when a bypass cap way on the other end of the board made a much
> > larger than expected difference.
>Would you mind elaborating on this? I could imagine a scenario where
>the power plane could be a source of AC noise - especially if components
>aren't bypassed adequately. The AC noise could then couple to the
>signal traces in its quest to complete a low impedance circuit. Is this
>what you observed, or am I way off?
>
>-Ethan
I don't want to come off as argumentative, but if you both think
about what has been said here, you can see the fallacy. If the
frequency of the noise is such that it can easily couple into a
signal trace, then that same noise would be well decoupled between
the power and ground planes and so would not be present to any
significant degree. The decoupling would not be through caps as it
would be from the very high frequency capacitance of the planes themselves.
Ground or power noise in circuits is nearly always due to
ground/power bounce and only affects the signals in or out of the
chip that has the "bounce" problem. Even if a board has inadequate
decoupling of the power plane, that noise is not going to
significantly couple into signals. Of course, because of the
ground/power bounce on the chip making the noise, its signals will
look like they are coupled to the noise because they are... but not
directly from the power plane to the signal traces, through the power
pins on the chip.
Rick
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
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