Re: gEDA-user: terminators

[Steven Michalske <smichalske@xxxxxxxxx>]

   On Apr 6, 2009, at 2:51 PM, [1]carzrgr8@xxxxxxxxxxxxx wrote:

     tune down your edge rate in the FPGA to make the effective

     bandwidth  of your edges lower. square waves are an infinite series
     of sine waves,

   trapezoidal are finite.  ( roughly speaking )

     3 inches is a 1/8th wave antenna for 500MHz,  again roughly (

     1GHz ~=

     12 inches ~=1 nS at the speed of light. )

     if you worried about signal integrity, ignore the logic analyzer

   Yeah but on a pcb, flight-time on FR-4 is around 170pS / inch (off the
   top of my head,
   anyway).   By way of 'rule of thumb' the trace looks like a
   transmission line if the flight
   time is greater than 1/4 wavelength.  If 1ns edge rate, then it's 1/4
   of 4nS, which
   translates into about 1" (I think I did that right).  So anything
   longer than 1" will have
   transmission line affects, and you should consider termination.

   my old timer gave me a different way....   use 1/8th wave antenna on
   PCB, and the speed of light.....  1/4 wave antenna open air....
   interestingly enough they are about the same, it's interesting to see
   the difference in rules of thumb.
   a 1ns edge rate if perfectly toggled looks like a sine wave (RC
   effects) that has just over 2nS period  or just under 500MHz
   500MHz on FR4 using your numbers of 170ps/inch, about 0.5C :-).
   From Mathematica, to keep track of my units.
   <<Units`
   Take 170 ps per inch and multiply it by 500 Mega Hertz
   (170. Pico Second)/(1 Inch) 500 Mega Hertz
   (85000. Hertz Mega Pico Second)/Inch
   What is per inches,  invert.....
   1/%
   (0.0000117647 Inch)/(Hertz Mega Pico Second)
   clean it up to inches, nice that Mathematica leaves all of the units
   in there :-)
   Convert[%, Inch]
   11.7647 Inch
   Make it a quarter wave antenna
   %/4
   2.94118 Inch
   How long you need to care after .... about 3 inches.
   So slow up your edge rate, with some source resistors or through your
   drive strength and other settings in the FPGA.
   now for the 1/8th wave rule of thumb
   <<PhysicalConstants`
   Lets look at the 1/8 th rule and speed of light
   SpeedOfLight /( 500 Mega Hertz)
   (149896229 Meter)/(250 Hertz Mega Second)
   Take it to inches
   N[Convert[%,Inch]]
   23.6057 Inch
   1/8th wave antenna
   %/8
   2.95071 Inch
   All rules of Thumb.....

   Xilinx fpga's are very capable of producing 1 nS edges or maybe
   better.  That translates
   to around 500 MHz.  My experience with the slew rate limiting on the
   spartan-2 is that it
   doesn't do very much.  Dropping the drive strength will definitely
   slow the edges since the
   output impedance of the gate goes up and you get an RC rise time
   affect on the line.  As
   long as the degraded rise-time is ok in your design, this is a good
   method.

   Check your ram's spec sheets,  also look at the additional delay that
   the traces on the far side will be exposed.
   longest clock Vs. shortest data and vice versa.
   You want your data eye to be nice and big,  the sampling clock right
   in the middle of it.  The cleaner the eye the slower your edge rates
   can go.

   gene
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References

   1. mailto:carzrgr8@xxxxxxxxxxxxx
   2. mailto:geda-user@xxxxxxxxxxxxxx


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