On Mon, 2011-04-11 at 23:59 +0200, Krzysztof KoÅciuszkiewicz wrote: > On Sun, Apr 10, 2011 at 11:22:54PM +0200, Markus Traidl wrote: > > > Actually I would like to use only the net attribute. There I could > > assign net=3V3 instead of net=3V3:1. > > > > I know that the ":1" is that the gnetlist tool knows that the 3V3 is > > connected to pin 1. > > > > But in case of a "One-Pin-Symbol" the gnetlist tool could assume that > > the only net should be assigned to the only pin. > > This has been asked for several times and I don't see a reason why this should > not be allowed for single pin symbols and only for pin number 1. > > The patches are attached - please test and report any potential breakage. I would advise a note of caution. In general, I don't like it when tools start special casing things like this.. it just feels wrong. This is a FAQ though.. The problem is that one can completely validly override nets for pins which don't exist in the symbol. (E.g. hidden power pins). People are proposing we add a new special case, which says "if the user omits the :1, assume a ":1" suffix when interpreting this particular attribute. If (and only if) the symbol has one single pin. What about the cases where this is a mistake? The net= attribute was supposed to refer to some implicit power pin - not the device's one symbolic pin, but the user forgot the suffix. Our power symbols already fell like a bit of a kludge as there is no physical pin or component which ends up in the netlist file. (Why should we have to give that power symbol's pin ANY pinnumber attribute? Why is pin 1 special?) Does special casing pin 1 as the "Missing ':?'" case help teach users how to use the net= attribute properly in the general case? I don't think so. _I_ think it adds to the confusion - as it would mean there are two completely different syntax for the same attribute to be used in different situations. I don't want to see that special case code proliferate in gEDA. We have enough already! A far more satisfying solution in the long run would be to make the symbols which annotate net naming (like the power and ground symbols, off-page labels etc..) have an editable attribute associated with the PIN which gets hooked up to the net which becomes named (or renamed). (netname=....) as if it were on the net its-self. I realise this isn't currently possible, as we have no means to set or override attributes on child objects of a complex (e.g. its pins). Aside.. For some tools (Xilinx's schematic editor springs to mind), the net name is a property of the net, and annotation markers you add are just graphical sugar around a visualisation of the net's name attribute. I'm not quite sure about whether power rail symbols transfer a name to nets they are attached to. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)
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