Re: gEDA-user: Attribute Net (without pin assignment) - for Powerand Port Symbols

[Wojciech Kazubski <wk0@xxxxx>]

> >
> >
> > > I would advise a note of caution.
> >
> > What some people do not like is the visible :1 in schematics -- can we
> > simple suppress that output for symbols with only one pin and digit 1
> > after the :
> > That would be a not too dangerous patch, because it concerns only
> > graphical output.
> >
> >
> +1
> Special case seems wrong. This would be a much nicer alternative.

Consider this one:

First, allow symbols to contain net segments, now this is forbidden in symbol creation guide.
Replace pins in power/gnd symbols with net segments, this segment can have label (and should have to be usefull).
If circuit parser encounters net segment inside symbol, it adds it to the net as any other net segment and sets a net name.
Any nets having the same name are assumed connected together (as is now).
This idea should work also for subcircuit ports and inter-scheet connections.

There is no need for special virtual components that do not have footprints.
The main problem may be the compatibility with current system.

Wojciech Kazubski


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