Re: gEDA-user: Clearing vias (Was: Last code sprint's IRC log and pictures)

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Mon, 2007-08-20 at 13:57 +0200, Christoph Lechner wrote:
> Peter Clifton wrote:

> But I'd guess it's the result of different implementations. Protel draws
> all those lines and circles that define the outline of the copper area
> using tracks with an user-definable width. pcb appears to use tracks
> that are infinitely thin. So you get problems.
> As you see in the attachment I've made (this is the PCB artwork in
> Protel 98) the circles around big pads look clumsy. Actually these
> aren't circles at all. When Protel fills an area with a polygon plane
> (this is how they call it) they compute and draw the outline of the
> plane first (and draw this outline using tracks with an given width) and
> then fill the plane with tracks. You can define
> 1) the track width
> 2) the grid size, i.e. the space between the tracks
> So here I set "grid size" < "track width" to obtain a closed fill.

I knew some packages used this technique of rasterizing with tracks to
form polygons, but I wasn't aware they made it this obvious to the user.
I guess setting the track width defines the end radius and size of
feature it will add though.

Once you've filled an area with polygon, can you still move things about
(and have the polygon re-flow), or do you have to rip it up and start
again?

I always find myself playing tricks with PCB (using separate polygons,
adjusting clearance on unrelated elements etc..) in an attempt to make
boards look "nicer" and have less of those infinitesimal tracks, and
other oddly shaped clearance leftovers. Perhaps I shouldn't worry so
much about visual appearance though!

I don't know enough about how PCB's internal geometric data-structures
or the new polygon code work to even postulate whether this kind of
behaviour is possible. Whether it could be done "fast" is yet another
question.

Peter




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