Re: gEDA-user: Clearing vias (Was: Last code sprint's IRC log and pictures)

[Christoph Lechner <cl0023@xxxxxxx>]

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Peter Clifton wrote:
> On Mon, 2007-08-20 at 13:57 +0200, Christoph Lechner wrote:
>> Peter Clifton wrote:
> 
>> But I'd guess it's the result of different implementations. Protel draws
>> all those lines and circles that define the outline of the copper area
>> using tracks with an user-definable width. pcb appears to use tracks
>> that are infinitely thin. So you get problems.
>> As you see in the attachment I've made (this is the PCB artwork in
>> Protel 98) the circles around big pads look clumsy. Actually these
>> aren't circles at all. When Protel fills an area with a polygon plane
>> (this is how they call it) they compute and draw the outline of the
>> plane first (and draw this outline using tracks with an given width) and
>> then fill the plane with tracks. You can define
>> 1) the track width
>> 2) the grid size, i.e. the space between the tracks
>> So here I set "grid size" < "track width" to obtain a closed fill.
> 
> I knew some packages used this technique of rasterizing with tracks to
> form polygons, but I wasn't aware they made it this obvious to the user.
> I guess setting the track width defines the end radius and size of
> feature it will add though.
Exactly. If you draw a track in Protel, its ends are "rounded"; it adds
a filled circle with diameter=track width to the end points


> Once you've filled an area with polygon, can you still move things about
> (and have the polygon re-flow), or do you have to rip it up and start
> again?
You can move things around as you like. Then once you need the polygon
rebuild, you double click the polygon plane and a dialogue pops up,
showing the parameters used when you first created that fill. Then you
click OK and it recomputes the plane. The baseline is that it isn't done
automagically at all, you have to do it as you want/need.
But my work flow as that I route all tracks on the PCB and when I'm done
I apply the polygon plane. This way, it's easy to see when you have to
swap two pins on a CPLD/FPGA etc.

> I always find myself playing tricks with PCB (using separate polygons,
> adjusting clearance on unrelated elements etc..) in an attempt to make
> boards look "nicer" and have less of those infinitesimal tracks, and
> other oddly shaped clearance leftovers. Perhaps I shouldn't worry so
> much about visual appearance though!
When doing some prototype boards, I never care about the appearance :)
Of course, "final" work should look "professional", whatever it is...

> I don't know enough about how PCB's internal geometric data-structures
> or the new polygon code work to even postulate whether this kind of
> behaviour is possible. Whether it could be done "fast" is yet another
> question.
Protel pours the whole copper plane in about 15 seconds on a Pentium III
800 MHz machine. Using 15mil wide tracks and 13mil grid size. So it
should be feasible to do it "fast enough".

Actually you can watch Protel doing it. First of all it follows all the
tracks and pads on the entire PCB with the correct spacing to form the
outline. Then it fills the area using 15mil tracks. The outline process
needs about 10 seconds, so the fill takes another 5 seconds to perform.

CU
- - C. Lechner
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