Re: gEDA-user: Yet another netlister

["A.Burinskiy" <alexbour@xxxxxxxxx>]

John,

It is not a big deal to write a parser. The big deal is creating 
meaningful language. Flexible enough, yet not overloaded with features, 
transparent and logical, understandable not only for designer, but to 
end user too. My problem is that I'm newbee for the PCB. Just started 
using commercial tool. And already very "happy" with that....
Over years I was busy with IC design and IC layouts. My last PCB design 
was shortly after graduation. So, I do have little knowledge of PCB 
community needs. I wrote netlister for IC community (or beeing precise  
- for me). If you could give me a hint on lang. semantic that would be 
usefull, I will gladly write parser. I think that gnetlist 
implementation is too heavy and not flexible enough. It depends too much 
on "device=" attr. For example, to determine whether something is 
netlistable or not it is enough to see whether it has isDef("refdes") && 
("device"!="none"). /*In reality I do some more checks*/, rather then 
writing semantic for each individual device. Special case - in/out 
terminals of subcircuit, that should parse there names to subcircuit 
nets... etc (One of the reason I decided to hardcode backend). 
Attributes could be filtered out, rather then verified against valid 
list one by one, as its done on gnetlist. All this little things allows 
to avoid extensive backend programming, when introducing new very simple 
device cause Guile/Schem study....

  Lets work on some universal netlister that will be accepted by both IC 
and PCB communities?

Alex.

On 08/10/2009 07:57 AM, John Doty wrote:
>
> I agree. But how it's to be *processed* depends on the needs of the
> netlist back end. It'd be nice, for example, to have a gnetlist back
> end that can extract the dependency graph for a hierarchical design.
> In the past, my tool for doing that has been a Japanese grad
> student. ;-)
>    



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