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Re: gEDA-user: wishful UI

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Subject: Re: gEDA-user: wishful UI
From: John Doty <jpd@xxxxxxxxx>
Date: Sat, 14 Aug 2010 17:06:13 -0600
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On Aug 14, 2010, at 4:57 PM, Paul Tan wrote:

> If the "split nets" means BUS, such as "addrBus[63:0]" which
> can be split into "addrBus[12:0]", "addrBus[15]", etc; or even
> the notion of Compound BUS such as "addrBus[63:0],ALE,CTRL",
> it can all be done with the backend scheme code. It really
> depends on the particular backend netlister implementation.

No, the issue here is that different segments of the same (single conductor) net may have different properties. Power nets are especially troublesome here. The segment between an IC and its bypass capacitor needs to be short. The segment at the output of the power regulator needs high current capacity...

Combining busses with net segment properties is probably beyond comprehension...

John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd@xxxxxxxxx

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References:
- Re: gEDA-user: wishful UI
  - From: John Doty
- Re: gEDA-user: wishful UI
  - From: Stefan Salewski
- Re: gEDA-user: wishful UI
  - From: John Doty
- Re: gEDA-user: wishful UI
  - From: Stefan Salewski
- Re: gEDA-user: wishful UI
  - From: Dietmar Schmunkamp
- Re: gEDA-user: wishful UI
  - From: Stefan Salewski
- Re: gEDA-user: wishful UI
  - From: DJ Delorie
- Re: gEDA-user: wishful UI
  - From: Stefan Salewski
- Re: gEDA-user: wishful UI
  - From: John Doty
- Re: gEDA-user: wishful UI
  - From: Paul Tan
- Re: gEDA-user: wishful UI
  - From: Andrew Poelstra
- Re: gEDA-user: wishful UI
  - From: Paul Tan

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