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Re: gEDA-user: wishful UI



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Am 13.08.2010 23:23, schrieb Stefan Salewski:
> On Mon, 2010-08-09 at 10:59 -0600, John Doty wrote:
>>  Remember, "pcb" isn't the only layout path we support.
>>
> 
> Yes. But I think the addition of net classes will not really break
> something. Of course it will increase the code size, which is not really
> nice. And it may decrease the working speed of PCB program.
> 
> I have written a short summary of this idea:
> 
> http://ssalewski.de/gEDA-Netclass.html.en
> 
> 
> 
> 
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> geda-user@xxxxxxxxxxxxxx
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> 

Stefan,

I looked at your suggestions about netclasses and I like them. What I
would like to add (and this adds complexity, too), is the notion of
differential pair (two wires should be same length, but the actual
length basically is a don't care) or busses and control signals
(industry standard SDRAM's etc where you have delay constraints of an
entire bus vs. a single control signal).
Furthermore I have a little objection towards " No chance for unskilled
people or autorouters", I agree with "unskilled people", but at least a
subset of the requirements can be translated to autorouter attributes,
e.g. impedance easily translates to geometry for a defined layer stack
(including base material, copper width ... ) while other attributes you
suggest ("short") would only be applicable to an autoplacer (or skilled
people).
I know that the target to add net classes AND to support them with
auto[route|place|...] is very challenging, but nevertheless I think that
it's worth a try/start a discusssion.

- -- 

Mit freundlichen Gruessen

Dietmar Schmunkamp
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