Re: gEDA-user: wishful UI

[John Doty <jpd@xxxxxxxxx>]

On Aug 14, 2010, at 4:57 PM, Paul Tan wrote:

> gnet-verilog.scm is the Verilog netlister, which already handle
> merging and splitting busses, and hierarchy. An example schematic
> files with generated Verilog netlist can be found in the attached
> zip file at:
> http://archives.seul.org/geda/user/Jan-2009/msg00056.html

You and DJ need to talk. He has his own proposal (http://www.delorie.com/pcb/bus-pins.html). But I like your use of the power of the existing tools.

John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd@xxxxxxxxx




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