Re: gEDA-user: wishful UI

[DJ Delorie <dj@xxxxxxxxxxx>]

> Sure, and the big EDA code based on LISP/Guile also uses syntax for
> names so a wire with such a name attrib seems to be all that's
> necessary to define a bus.  Putting the syntax netname[0:7] into
> form netname[0], netname[1], ....  for the backends is fine.  Seems
> to me the common code would still need to be aware of bus nets.

I published my paper mostly to get a discussion going on what busses
*mean* though, not the implementation details.  For example, what does
it mean when three busses with different names are connected?

 D[15:0] ======**==== D[15:0]
               ||
               \\==== A[1:16]

With nets, it breaks if you do that.  I would want DRC to complain to
- it's a real error to give one signal two names.  Do we need a
separate "bus thing" in order to apply different rules?

And I want to understand the implications of pins that reflect
multiple signals, too - mapping names and numbers, etc.


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