Re: gEDA-user: wishful UI

[Armin Faltl <armin.faltl@xxxxxx>]

DJ Delorie wrote:
> > Sure, and the big EDA code based on LISP/Guile also uses syntax for
> > names so a wire with such a name attrib seems to be all that's
> > necessary to define a bus.  Putting the syntax netname[0:7] into
> > form netname[0], netname[1], ....  for the backends is fine.  Seems
> > to me the common code would still need to be aware of bus nets.
> >     
>
> I published my paper mostly to get a discussion going on what busses
> *mean* though, not the implementation details.  For example, what does
> it mean when three busses with different names are connected?
>
>  D[15:0] ======**==== D[15:0]
>                ||
>                \\==== A[1:16]
>   
The problems I see with this are:
* 2 names for the same bus are probably confusing for a user
* if busses of different name are allowed to connect, they should have 
the same wire layout
* if they really shall look like above, the number of wires must be 
equal and the obvious
 mapping mechanism must be in place

If all this is not for you, would it be possible to make a 
bus-mapper/connector symbol?


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