Re: gEDA-user: Subnets

[Stefan Salewski <mail@xxxxxxxxxxxx>]

On Sun, 2010-08-15 at 14:10 -0400, Rick Collins wrote:
> I see we are talking about two different things.  I was responding to 
> Andrew's post about splitting nets into portions with different 
> properties.  In my way of thinking if they have different properties, 
> they should be separate nets.
> 
> I see that your example of Power/Bypass we are talking about one net 
> with different properties.  Ii think it will be hard to convey the 
> intricacies of power supply bypassing to an autorouter.  One thing I 
> find interesting is how in an example you say the two subnets can 
> only join at P1.  How do you define P1?  To me this is the point 
> between two separate nets... which is really what you are 
> describing.

I have to admit that I do not know much about how all that netlist stuff
is handled in gEDA/PCB. For the example of Power/Bypass subnets and
Point P1: The intention is to have (enforce) a short, low impedance
connection from OpAmp power pin to a pin of the bypass capacitor. A good
layouter will always ensure this. My idea was to split the whole 5V-plus
net in segments or subnets (with same netname, but different
attributes/class). For my picture P1 is a common point of these subnets.
One restriction is: This subnet with property bypass shall be short, low
impedance. For this case it is a connection of only two points, which
makes it very simple. A human layouter can understand it, and we should
be able to transfer this information to PCB program, so that DRC can
verify correctness. I can imagine more difficult cases. One is the
"Short" net from capacitor pin to GND symbol. GND symbol does not really
define a pin. One interpretation may be to translate it to a short trace
to a ground polygon. An other problem is a subnet with property "short"
which is built of multiple segments -- how will we define
"trace-length<6mm" for this case. Maximum distance of pairs of pins for
this net? All this are details, which we can define later.
Maybe a more difficult problem is to make nets compatible, so that a
minor net is allowed to connect at an arbitrary point to a mayor net.
For example a net (default net class) carrying a plain +5V signal to
some static logic input should be allowed to connect at an arbitrary
point to the fat +5V net. We do not need these concept of compatible
nets, but is would be nice to have. (compatible in this case means
compatible in only on direction. We have the fat traces from the DC_DC
converter to big fat capacitor and high current devices (DRC will check
if all these connections are of class/attribute "fat"), but other low
order nets with same netname can connect at arbitrary points.)     

Of course, all this is not easy. But interesting, and we have some
really smart people on this list...

Best regards,

Stefan Salewski




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