Re: gEDA-user: Subnets

[Stefan Salewski <mail@xxxxxxxxxxxx>]

On Sun, 2010-08-15 at 21:03 +0200, Stefan Salewski wrote:

> attributes/class). For my picture P1 is a common point of these subnets.
> One restriction is: This subnet with property bypass shall be short, low
> impedance.

Sorry, I forgot:
Points which connects subnets will be always pads or pins on PCB board
(pins of devices). By physical design we always define properties for
traces between device pins, it makes no sense to change trace properties
somewhere between device pins (if it makes sense, then that is a special
case, like antennas, which is beyond our proposal).

So location of point P1 is well defined, in schematic, and in layout.
(But there is no need to call it P1, or give it a special name, it is
simple a common node of two subnets with same netname.)





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