Re: gEDA-user: Subnets

[Stephan Boettcher <boettcher@xxxxxxxxxxxxxxxxxx>]

Stefan Salewski <mail@xxxxxxxxxxxx> writes:

> On Mon, 2010-08-16 at 10:09 +0200, Stephan Boettcher wrote:
>> John Griessen <john@xxxxxxxxxxxxxx> writes:
>> 
>> If there is work put into partitioning a layout, can't we please have
>> hierarchical layout instead?
>> 
> I have still problems to understand the goals and benefits of
> partitioning hierarchical layout on PCB board level. Can you give an
> example, when possible with a picture?

I usually have hierarchical schematics with multiple instances of the
same subcircuits referenced from the main page.  The deepest until now
were three layers of hierarchy.

All the cutting, sed-ing and pasting of the subcircuits to multiple
instances, with replication of later changes on all copies is pretty
unflexible.

Hierarchical sub-cells (like with ASIC layouts) would allow to make and
maintain such circuits much easier.

What I am asking for here is, when you now talk about layout
zones/partitions/whatever it's called in the end, please consider the
application of the concept for this kind of hierarchy.  Maybe the new
concepts can be easily applied for that as well, with a little vision
into that direction.

Maybe it is trivial to allow multiple copies of a layout zone on a
board, with a common netname/refdes prefix substituted on the copies.
When you edit the layout of any copy, all instances follow the change.

My eagle-using colleagues envy me for the hierarchical schematics that I
can draw in gschem.

-- 
Stephan


_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user