Re: gEDA-user: Layer selective DRC

[Sparky <scopaev@xxxxxxxxx>]

Levente Kovacs <leventelist@...> writes:

> 
> If you add the attribute
> 
> PCB::skip-drc
> 
> to a layer, that won't be checked against DRC, and commections.
> 
> Levente
> 
> On Wed, 3 Aug 2011 23:56:23 -0700
> Colin D Bennett <colin@...> wrote:
> 
> > On Thu, 04 Aug 2011 01:48:09 +0200
> > Kai-Martin Knaak <kmk@...> wrote:
> > 
> > > Colin D Bennett wrote:
> > > 
> > > > A feature I have heard previously requested is to be able to mark
> > > > certain layers as âno-DRCâ.  For instance, to allow special trace
> > > > elements such as antennas that the DRC thinks are incorrect shorts
> > > > between two nets.
> > > 
> > > These should be omited from update_rats, rather than be ignored on
> > > DRC. The DRC as it is currently implemented, does not check for
> > > correct connectivty. It does not detect a short.
> > 
> > Oh, that's right.  I forgot since I tend to consider the Optimize Rats
> > action and its feedback as a first pass of DRC, and the actual DRC
> > action as a more detailed pass... but it seems like it would be ideal
> > for a short to be detected by DRC.
> > 
> > > I think, this
> > > functionality would be best implemented with a flag
> > > "don-t-check-connectivity" added to the object. Put these antennas
> > > in a separate layer and make DRC special for this layer would still
> > > feel like a crutch.  
> > 
> > My current workaround is to actually connect the antenna input
> > directly to ground on the schematic, so that pcb does not complain
> > that the PCB trace antenna is a short.  (See attached figure from the
> > schematic.)  For this specific and simple purpose, this works well
> > enough for the moment.
> > 
> > Regards,
> > Colin
> > 
> 
> 

My outline layer has thin line widths (0.1mm) that are being compared to the
copper width by the DRC.

I keep getting the "Line width is too thin" DRC error (code is in find.c).

I downloaded the latest git code (2011-08-05) compiled it, ran it, all looks
normal, except for the above error when I do a DRC check.

For my outline layer I did the following to add the attribute:
  Edit->Edit attribute of->CurrentLayer
  Left box:  PCB::skip-drc
  Right box: 1

Am I just entering the attribute incorrectly?  Any guidance would be appreciated.

Thanks,
Sparky



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