Re: gEDA-user: Foss-pcb Proposed plan from CERN

[John Doty <jpd@xxxxxxxxx>]

On Aug 25, 2011, at 6:33 PM, Dietmar Schmunkamp wrote:

> - From my point of view the major thing is to have one design source (even
> with a multitude of attributes e.g. net_group = g1, net_length(g1) = xxx
> mm, tolerance(g1) = 1 mm, ...etc) and drive simulation and board layout
> from this single source. That also requires feedback of electrical
> properties of the board wires back into the design source (and by this
> into the simulation model).

I think the back-annotation approach is complex, messy, and has lots of problems.

For my ASIC design work, the layout contractor generates the final simulation netlists using the layout software (Calibre). I then compare simulations of that netlist with simulations of the (enormously simpler) netlist derived directly from the gEDA schematics. An actual schematic derived from the layout would be incomprehensible: all hierarchy is flattened and parasitic components vastly outnumber the intended ones.

I think the same considerations apply to boards: it would be good for the layout tools to be capable of generating simulation netlists. It doesn't make sense to me to to run the layout data back through schematic capture tools to get to simulation.

John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd@xxxxxxxxx




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