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Re: gEDA-user: Foss-pcb Proposed plan from CERN
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Am 26.08.2011 15:50, schrieb John Doty:
>
> On Aug 25, 2011, at 6:33 PM, Dietmar Schmunkamp wrote:
>
>> - From my point of view the major thing is to have one design source (even
>> with a multitude of attributes e.g. net_group = g1, net_length(g1) = xxx
>> mm, tolerance(g1) = 1 mm, ...etc) and drive simulation and board layout
>> from this single source. That also requires feedback of electrical
>> properties of the board wires back into the design source (and by this
>> into the simulation model).
>
> I think the back-annotation approach is complex, messy, and has lots of problems.
>
> For my ASIC design work, the layout contractor generates the final simulation netlists using the layout software (Calibre). I then compare simulations of that netlist with simulations of the (enormously simpler) netlist derived directly from the gEDA schematics. An actual schematic derived from the layout would be incomprehensible: all hierarchy is flattened and parasitic components vastly outnumber the intended ones.
>
> I think the same considerations apply to boards: it would be good for the layout tools to be capable of generating simulation netlists. It doesn't make sense to me to to run the layout data back through schematic capture tools to get to simulation.
>
> John Doty Noqsi Aerospace, Ltd.
> http://www.noqsi.com/
> jpd@xxxxxxxxx
>
>
>
>
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John,
I think we share a common goal and want to achieve that by different
means: You want to put the generation of the simulation input deck to
the layout tool while I prefer having it closer to the beginning of the
design, in the schematics. I think there are pros and cons for both
options, I'm in favour for having much as information as possible in the
design entry because there it eases reuse if applied correctly.
Let me give an example: In the 'original' schematic a net between 2 or
more points is a solid connection. on the pcb it gets a (tapped) lossy
transmission line (of course depending on the operating frequency). With
repect to reuse I prefer having that information attached to net
attributes and generate a simulation (gnucap) input deck as well as
establish constraints to the board layout tool.
PS: In my day job I'm working on ASICs, too, but the logic input is
purely vhdl. To verify that a pre-PD netlist matches a post-PD netlist
we use boolean eqivalence check (works also for vhdl to synthesized
netlist comparison). Timing is verifed by statical timing analysis (no
simulation). That's possible because the wire length is far from
transmission line effects (length vs. max freq) Cross coupling between
nets is taken into account, too.
- --
Mit freundlichen Gruessen / Best regards
Dietmar Schmunkamp
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