Re: gEDA-user: uEDA .. was .. Re: Heavy Symbols and such

[al davis <ad151@xxxxxxxxxxxxxxxx>]

On Thursday 06 December 2007, Peter Clifton wrote:
> Al previously explained how this could also be used to model
> PCB tracks, where the simple model could be that they are
> wires (or short circuits), and with more complex models being
> substituted based on their physical geometry if desired.
>
> I don't personally see how this accounts for inter-track
> capacitance, or inductive coupling... so I'm stopping
> somewhat short of suggesting VHDL as the "one true format"
> for specifying a board layout, but please don't dismiss the
> format's possibilities.

It doesn't, directly.  There is enough information to easily 
simulate transmission line effects, but without crosstalk and 
radiation.  Static timing analysis is easy.

For crosstalk, it is necessary to analyse the relations between 
the traces, which is not easy.  Using a standard language makes 
it easier, because the extractor can be written in general, as 
opposed to for a particular layout program.  As I said, it is 
still not easy.

Designing the extractor around a particular tool's own format is 
a bad idea because then they are forever tied.



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