Re: gEDA-user: uEDA .. was .. Re: Heavy Symbols and such

[al davis <ad151@xxxxxxxxxxxxxxxx>]

On Thursday 06 December 2007, Peter Clifton wrote:
> XML can be an expressive "format" if you use it right (define
> a good DTD to use for your application), so I'm not saying
> VHDL / Verilog are the only solutions.

An XML based format could have an "advantage" (in quotes because 
whether it is an advantage or not is a matter of opinion) that 
it is equally foreign to all.  VHDL and Verilog are likely to 
be supported directly by simulation and synthesis tools.

> Are the standards for both (or either) freely available,
> without paying money? That would be a real selling point for
> me.

VHDL-AMS - for a price.
Verilog-AMS - free download. ("abridged" but complete enough) 
http://designers-guide.org/VerilogAMS/VlogAMS-2.2-pub.pdf

> SPICE.. is there a standard?

Answer #1:
No.

Answer #2:
Yes, there are lots of them, all different.

Practical answer:
There is a subset that is so common it can be considered to be 
standard.  It is essentially the format of Spice-2g6, without 
POLY.


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