Re: gEDA-user: uEDA .. was .. Re: Heavy Symbols and such

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Fri, 2007-12-07 at 08:35 +0900, John Doty wrote:

> The issue at hand is how the databases that drive this should work.  
> Various people have various visions. I have no strong preference as  
> long as the result retains gEDA's flexibility. But I don't know how  
> to evaluate Al's suggestion, as it's just "wave the magic Verilog  
> wand, and all will be well".

I don't think Verilog was ever proposed to be the database, but the
analog variants of VHDL and Verilog do represent quite expressive
file-formats for defining hierarchical circuitry and systems.

Peter B and I designed some data-structures based on gnetman's some time
back. It was mostly a thought exercise, and served to help us understand
more about how gnetman (and netlisting in general) works. These are the
sorts of data-structures and databases which exist in CPU memory, and
can be easily exported to various formats. Spice / VHDL / Verilog to
name three.

The point about the latter two which make them interesting, is that they
don't special case primitives like resistors, inductors etc.. At each
level of hierarchy, the sub-blocks / circuits below are just
implementation details. Properties can be attached to sub-circuits..
(generics? (its been a while since I used VHDL)).

A resistor might be two nodes with an ideal V=IR relation, or it might
be a model for the "X" brand wire-wound resistor, with a dissipation
model tracking its thermal state, R dependant on temperature, series L,
inter-turn capacitance etc..

Al previously explained how this could also be used to model PCB tracks,
where the simple model could be that they are wires (or short circuits),
and with more complex models being substituted based on their physical
geometry if desired.

I don't personally see how this accounts for inter-track capacitance, or
inductive coupling... so I'm stopping somewhat short of suggesting VHDL
as the "one true format" for specifying a board layout, but please don't
dismiss the format's possibilities.

XML can be an expressive "format" if you use it right (define a good DTD
to use for your application), so I'm not saying VHDL / Verilog are the
only solutions.

Are the standards for both (or either) freely available, without paying
money? That would be a real selling point for me.

SPICE.. is there a standard?

Best wishes,

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)



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