Re: gEDA-user: uEDA .. was .. Re: Heavy Symbols and such

[Steve Meier <smeier@xxxxxxxxxxxxxxxxxxx>]

John,

Well veralog or vhdl as an internal data structure format? Maybe but I
am not going to worry about it or attempt it. But I am curios enough
that I might look at icarus' data structures. Perhaps what Al is
suggesting is that vhdl has all the elements needed for constructing an
internal data structure? again maybe, but it seems that geda has a
pretty good selection as well and if libgeda is missing something then
extending libgeda at this point might be easier or in my opinion at
least my non-stock library. As I start to dig into the capabilities of
these languages it might become apperent that an extension is desirable.
Whats that old saying something about if you want to understand a
language learn a few?

As I recall John you have consistently argued for a spice output for at
least modeling purposes if not as a netlist format for chip and perhaps
even board layout? So yes your help on spice syntax would be
appreciated. Also as part of this process I am striving to create a well
documented scheme interface into the library review of that interface
and suggestions on what is needed to achieve the desired spice, vhdl,
verilog output files would also be apreciated. If you really feal like
it then once the scheme interface is deffined you could take a shot a
writting/modifying the spice output format macro.

Later on today I will send out the latest scheme interface document it
still mostly (almost exclusively) is about getting data into the library
structures but I am about to turn my attention towards basic netlist 
generation control (page level and  as specific command to flatten the
page nets/buses into a single page as a specific command) and schematic,
symbol, bom and netlist exporting functions. Actual netlist generation
both page and flattening functions already exists in the library as does
the scheme interface at least for the flat netlist but these scheme
functions havn't made it into my document yet.

Then with an eye towards the future I am starting to think about how one
could embbed files other then schematics into symbols. As well as spice
models these could include hardware description languages such as
verilog and vhdl and???

Thanks,

Steve Meier


John Doty wrote:
> On Dec 6, 2007, at 3:13 PM, Steve Meier wrote:
>
>   
>> John,
>>
>> The beauty of geda and its scheme capabilities is that any file format
>> that is reasonably well deffined can be supported.
>>     
>
> Indeed. Give me a well defined format with a clear use, I might even  
> help.
>
>   
>> Instead of railing at at Al start helping to nail doen the  
>> deffinitions
>> on the formats your prefer.
>>
>> As I have said my short term goals are to provide output support for
>> verilog, vhdl and spice.
>>     
>
> But that can mean many things. Al keeps talking about Verilog as an  
> internal format, not an export format. But it's impossible to  
> understand what he means by that.
>
>   



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