Re: gEDA-user: blue sky ideas - written down finally

[DJ Delorie <dj@xxxxxxxxxxx>]

> I think you are advocating the logical view schematic (as opposed to
> a physical view).  BTW, John Doty does this for his connectors - as
> I recall.

If the chip was a single "gate" then a physical view could make sense.
But when a chip is multiple gates, and you have the option of swapping
which chip a specific gate comes from, a "physical view" becomes
difficult to render.

> Personally, the physical view seems to cover the largest group.
> Yeah, large FPGA or uP don't fit very well on the sheet.  Maybe
> that's a place where your method works out.  It seems to work for
> John Doty and connectors.  You just don't want to get to the point
> where you'd be better off with just a netlist - which totally
> defeats the purpose of a graphical entry system.

Physical view works for physical devices, like connectors or sometimes
chips.  I've seen schematics where the chip's symbol was a block with
the pins laid out like the physical device.  I'd rather have the pins
grouped by function in some logical layout.

But when you've got something like a 7400, a physical view is
difficult to justify.  It's much more useful to sprinkle NAND gates
around the page, and have some other way of mapping them to a physical
device.

HOWEVER, my pin mapping scheme doesn't imply either way.  You could do
pin swapping on a non-gate symbol (like RAM) and you can still do
visible power pins on a NAND gate.  You can probably figure out a way
to do "gate" swapping on a non-slotted part (like IEC bundled nand
gates, or octal latches).  The only thing that would be deprecated is
the hidden netlist connections; they'd become visible somewhere.


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