Den 2010-12-31 15:40:39 skrev John Griessen <john@xxxxxxxxxxxxxx>:
On 12/31/2010 08:02 AM, Stephen Trier wrote:I was wondering whether there would be a demand for this style of logic symbol in gschem.Most logic designers now use verilog blocks for such logic and never even make a diagram with visual cues like IEEE symbols have.
In the US or in the whole world?As I am not a logic designer, but rather a guitar player, I guess I could use whatever symbols I like, rightâ? ;P
Since much low level logic is synthesized for chips or FPGAs these days, and there is often a way to probe signals anywhere, the meaning conveyed by control wires as in up, down, clr, is only made more obvious when using probes or verilog testbench code.Making function visually obvious seems to be skipped since just afterIEEE symbols were proposed in the 70's. Except for TIs discrete logic parts.John
-- Kind regards Johnny Rosenberg _______________________________________________ geda-user mailing list geda-user@xxxxxxxxxxxxxx http://www.seul.org/cgi-bin/mailman/listinfo/geda-user