Re: gEDA-user: pcb insulator layer

[John Griessen <john@xxxxxxxxxxxxxx>]

Peter Clifton wrote:
> On Wed, 2008-02-06 at 11:14 -0500, DJ Delorie wrote:
>>> That is really black magic. How long has it done that? I've never
>>> noticed!
>> What, putting the outline on the ps plots?  It's the age-old "draw
>> outline" option, I just fixed it to draw the actual outline layer if
>> you have one.
> 
> That's pretty cool. I looked at output logs for a set of gerbers
> produced with a commercial PCB tool, and it seemed that they had output
> gerbers which combined from multiple internal layers.
> 


Now I halfway understand that code.  I found the test done on all copper layers
to see if they have a special name and added my case, a name that starts with insul
so it could be insul-top or insulator and that named layer now skips drawing vias and pins.

That helps make a useful gerber output layer for putting down insulating paint -- probably by
silk screening, not certain yet.  But this lets my fab do carbon jumper and silver jumper
with very few drilled holes.

Anyone know of some good wire terminal connectors that grab the board edge for strength,
yet only mount by SMT solder?  Then I'd have NO holes on one of my boards.


  diff ../../pcb06feb2008/src/draw.c draw.c
900c900
<         || strcmp (Layer->Name, "route") == 0)
---
 >         || strcmp (Layer->Name, "route") == 0 || strncmp (Layer->Name, "insul",5) == 0)


Does metal included on vias for all layers help plated through holes?

John Griessen

-- 
Ecosensory   Austin TX


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