Re: gEDA-user: analog/code co-simulation and schematics and netlists for silicon

[Geoff Swan <shinobi.jack@xxxxxxxxx>]

I have daydreamed about the possibility of linking gEDA with qucs and
simavr/gdb for example. To be able to create a circuit layout and
perform harmonic ballance simulation combined with microcontroller
code simulation... Oh, and while I daydream, an integrated tool for
doing FEM analysis the pcb design to improve RF circuit layout. I am
only new to gEDA so forgive me if I some of this is already possible..
From the little I have seen getting the circuit information out of
gEDA must be fairly straight forward - it is getting the other tools
to play nicely that would be tricky. This is something that I
certainly would like to look into.

Geoff

Australia

On Wed, Feb 24, 2010 at 4:49 AM, John Griessen <john@xxxxxxxxxxxxxx> wrote:
> al davis wrote:
>>
>> I proposed a translator system, using an intermediate language, to
>> translate both ways between schematic, layout, and simulation.  It needs to
>> happen.
>
> I've got a phone call to Reid Wenders of Triad scheduled this PM.
>
> Anyone have any ideas you'd like mentioned to him?  Questions I should ask?
> I'm just planning on telling him the status of verilog-ams backend of
> gnetlist and that it can run some simulations from a netlist -- the way it
> needs to be for many chip design/verification work flows.  Just in case
> there's
> any development money or new developers available.
>
> Reference:  http://www.edn.com/article/CA6670945.html
>
> “We have been working with Keil to simulate mixed-signal peripherals. But,
> eventually, we are going to need a full analog/mixed-signal simulator on the
> desktop—something that can pull together Verilog, Spice, and software
> simulations on the desktop for a low price,” he says. “We are still
> searching.”  Reid Wenders EDN, 7/23/2009
>
> John Griessen
> Ecosensory   Austin TX
>
>
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