Re: gEDA-user: PCB suggestion

[Mike Jarabek <mjarabek@xxxxxxxxx>]

harry eaton wrote:

> It's not true that pcb has a "fundamental" limit of 8 layers. There are 8
> copper layers. There are TWO silkscreen layers IN ADDITIONto the 8 COPPER
> LAYERS. You can draw lines, arcs and polygons on the silk layers. It's
> fairly straightforward to add several non-copper layers for things like
> keep-outs, outline, or the mask layers. The hard part is implementing the
> functionality associated with those layers. It's more of a "fundamental"
> limit to go beyond 8 copper layers but then nobody has ever, to my
> knowledge, built an 8 layer board with pcb. I know of a few 6 layer boards,
> many 4 layer boards, tons of double-sided boards and few single-sided boards
> but nothing beyond 6 layers.  It is rare indeed that more than 8 copper
> layers are required. Usually when 10 and 12 layer boards are made it is
> because the designers are lazy.
I'd like to add a data point to Harry's comment, we made an 8 layer 
board with PCB, it was approximately 10"x10".  The 900 pin BGA device 
drove up the layer count.  We needed six signal layers to break out the 
device, plus two power planes.  Ideally, we would have had another 
couple of power planes for signal integrity, but this was a prototype 
test card and had very slow edge rates.

More copper layers would have been very handy indeed.

The last board we did (using commercial tools, unfortunately) had 18 
layers.  It had close to 5000 nets, we had no choice but to use the 
auto-router. Despite our best efforts, the autorouter would not 
converge, with the signal integrity rules we had set, with anything less 
than 14 or so routing layers.  If anyone is lazy, it's the CAD vendor 
who's autorouter still only does Horizonal/Vertical routing, and not 
diagonal routing.  ( And we, collectively, know how to do something 
about that! ;-)


Mike

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                             Mike Jarabek
                               FPGA/ASIC Designer
http://www.istop.com/~mjarabek
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