Re: gEDA-user: PAL/CPLD programming

[William Dieter <william.dieter@xxxxxxxxx>]

On Wed, 12 Jan 2005 08:27:17 -0800, Stephen Williams <steve@xxxxxxxxxx> wrote:
> As Charles pointed out, it would require some C programming skill
> and knowledge of logic minimization. The Icarus Verilog synthesizer
> takes care of allocating registers, but the netlist of logic that
> it produces needs to be converted to sum-of-products that PLDs
> take. It would, for example, make a good undergrad EE mid-term
> project, or an experienced EE could do it in a week or so. That is,
> an experienced EE with the time to spare:-(

The time is always the tricky part.  Unfortunately I don't have any
spare cycles right now, and I am not teaching a class for which it
would be appropriate this semester. I will add it to my list of
projects for students (or me, if I get the time) to work on.

> It would be nice to get IPAL finished up, as this seems to be
> a niche in need of filling after all.

-- 
Bill Dieter.
Assistant Professor of Electrical and Computer Engineering
University of Kentucky
Lexington, KY 40506-0046