Re: gEDA-user: trace calculation

[joeft <joeft@xxxxxxxxxxxxx>]

DJ Delorie wrote:

> > Why? Via doesn't have much more inductance than a piece of trace,
> > does it?
> >    
>
> At high enough frequencies, traces are waveguides, not just
> conductors.  Vias have nontrivial geometry relative to the signal.
>
> That reminds me of another optimization I'd like to implement in the
> future.  Instead of corners, treat all traces like elastic bands, so
> that they end up as sweeping curves (lines+arcs) with no corners at
> all (except for 3-trace nodes).  I want this myself just because it
> makes the board look pretty, but I wonder if gentle curves provide
> better waveguide performance than corners?
>
>
>  
Indeed, vias can have a serious detrimental effect.  The most simple 
case is to model the via as an inductor.  If you account for the 
capacitance of the outside layer pads you now have a more complex 
problem.  Then you can account for the pad-to-plane capacitance as the 
vias pass through inner layers...and so on.  A simple (shunt C) - 
(series L) - (shunt C) model does quite well up to a few GHz.

Going around a corner with a tapered or narrowed trace is significantly 
better than a simple square corner.  A swept curve (especially when the 
radius is more than a few line widths) is even better, and gives pretty 
good results although you still get a *slight* reduction in impedance 
due to the excess capacitance in the curve.

I wouldn't worry about dealing with all direction changes as 
sweeping/curved bends:
-You would need to have some way for the program to in advance how much 
angle (arc)  you wanted to cover.
-You can probably pack more traces in when routing manually only at a 
n*45 degree angle.
-Autorouting and DRC calculations would probably get more messy.

Joe T.