Re: gEDA-user: Test pads in PCB

[David Hart <dhart155@xxxxxxxxxxx>]

On Mon, 2006-01-16 at 07:34 -0500, Stuart Brorson wrote:
> As long as people are discussing vias in PCB, I'll raise a different
> question which occurred to me recently.
> 
> Modern electronic manufacturing methods often include a testing step
> in which the stuffed board is checked for connectivitiy using either a
> "bed of nails" test fixture, or with a "flying probe" robotic
> probe.  These tests are totally automated, and are performed by very
> expensive machines manufactured specifically for testing PCBs.  Both
> types of test use little brass probes which look like pogo sticks 
> to touch little round pads you attach to each and every track.  These
> round pads are maybe 30 -- 50 mils in diameter.  The pads live only on
> the surface metal layers, and the soldermask is cleared away from the
> pad so that the probe may make contact.  Using these pads and your
> netlist, the machines can verify that your newly assembled PCB doesn't
> have any shorts, connections are correct, etc.  [1]
> 
> So my question:  Has anybody here tried placing test pads on their
> PCBs?   I have a feeling most people using PCB are doing so for
> hobby/student projects.  However, professional-level boards destined
> for mass manufacture need this feature.  I suppose one could just
> create a "testpad" element in PCB to place & hook to every
> net.  However, since the test pad doesn't appear in the netlist, PCB
> will complain every time you refresh the netlist, and it will make DRC
> checking a real PITA.  Therefore, I have a feeling that any testpad
> element needs to be recognized as a special structure by PCB. 
> 
> Any thoughts?  Has anybody tried to place testpads for manufacturing
> test?  
> 
> Stuart
> 
> [1]  Note:  The test pads I am talking about are *not* test points
> which you place in your circuit to hang scope probes off of.  They are
> used more or less exclusively by your PCB assembly house for ICT -- in
> circuit testing.  

OK. You guys have struck a nerve, and caused me to pull out my trusted
"Printed Circuits Handbook, 5th Edition" by Coombs. The following
chapters of the book address:
  Chapter 38 -- Bare Board Test Methods
  Chapter 39 -- Bare Board Test Equipment

Test points and board test issues you may wish to consider (after a
quick read of the above):

1) First do visual inspection (the human eye picks up a lot).

2) Then do an automatic optical inspection (not all board houses are
prepared to do this step).

3) Then do the DC continuity test, from component pad to component pad.
If a net has n nodes, there are a minimum of n-1 tests. If the component
is buried (e.g., a buried resistor with no external copper pad, then
bring out a test pad/point.

4) Where warranted, and called out in the Fab instructions, the
continuity resistance threshold can be called out as a Fab requirement.
Probably somewhere in the IPC standards (my old copy of Coombs lists a
few) that are referenced in the Fab instructions. The idea is to limit
allowed maximum trace continuity (e.g., trace length).

5) Then do a DC Isolation test, to verify there is adequate electrical
isolation between nets that are not intended to be connected. Again,
called out in the Fab instructions, probably in some IPC standard, are
requirements for minimum isolation resistance and applied voltage. With
aggressive trace/spacing geometries, and traces stacked close to each
other, this is a hard spec to call out. Coombs goes into detail on how
geometries can effect pass/fail. The result can be either hard shorts or
leakage failures.

Here is where adding test pads can be useful in the manufacturing
environment. Simply connect to the test pads to test the isolation
between two nets. Potentially saves a lot of time.

6) Does your design use buried components (e.g., buried resistors)?

7) Does your design use multiple planes, and need testing for capacitive
or electromagnetic coupling.

8) High-speed designs may call out testing with Time Domain
Reflectometry (TDR), to confirm there are no discontinuities in the RF
impedance level along a conductor, resulting in reflected voltages.
Typically "required" for 1GHz and above digital designs. This is part of
the recent discussion about vias and their effect on impedance.

9) Production volume. Small quantities typically use flying-probe tests,
large quantities usually justify building dedicated test fixtures. The
testing options are not always available for both test methods at the
board house.

For the above issues the appropriate IPC specs that your board house
uses for standard manufacturing capabilities are a good start for
understanding how testing is done. Unfortunately, I no longer have
access to IPC documents, they are too expensive.

Also, a good long talk (or e-mail) with your board house rep can help
you decide what to do.

I want to thank the members of this list for bringing up this subject. I
just sent an e-mail to my board house asking just these kind of
questions.

Dave...