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Re: gEDA-user: GND vs. PGND
On 09 Jan 2007 18:13:35 +0100, David Kuehling <dvdkhlng@xxxxxx> wrote:
Hi,
I used both (analog) GND and PGND symbols in my layout. Now after
running gschem2pcb and loading the netlist file I see that those symbols
create two separated nets.
Still I want to connect GND and PGND somewhere in my layout without
making the DRC complain. I tried to add a connection between GND and
PGND in my schematic, but that doesn't help.
If you attach two named nets to a component pin they will connect.
See my simple example below.
(* jcl *)
--
http://www.luciani.org
----------------- cut here -----------------
v 20050313 1
C 74600 61000 1 90 0 EMBEDDEDresistor.sym
[
L 74400 61600 74600 61500 3 0 0 0 -1 -1
L 74600 61500 74400 61400 3 0 0 0 -1 -1
L 74400 61400 74600 61300 3 0 0 0 -1 -1
L 74600 61300 74400 61200 3 0 0 0 -1 -1
T 74200 61300 5 10 0 0 90 0 1
device=RESISTOR
L 74400 61600 74600 61700 3 0 0 0 -1 -1
L 74600 61700 74500 61750 3 0 0 0 -1 -1
P 74500 61900 74500 61750 1 0 0
{
T 74450 61800 5 8 0 1 90 0 1
pinnumber=2
T 74450 61800 5 8 0 0 90 0 1
pinseq=2
}
P 74500 61000 74500 61152 1 0 0
{
T 74450 61100 5 8 0 1 90 0 1
pinnumber=1
T 74450 61100 5 8 0 0 90 0 1
pinseq=1
}
L 74400 61201 74500 61150 3 0 0 0 -1 -1
T 74600 61000 8 10 0 1 90 0 1
pins=2
T 74600 61000 8 10 0 1 90 0 1
class=DISCRETE
]
{
T 74300 61400 5 10 1 1 180 0 1
refdes=R1
T 74600 61000 5 10 0 0 0 0 1
footprint=0805
}
N 74500 61000 74500 60800 4
N 74500 60800 73800 60800 4
{
T 73800 60800 5 10 1 1 0 0 1
netname=GND
}
C 75600 61000 1 90 0 EMBEDDEDresistor.sym
[
L 75400 61600 75600 61500 3 0 0 0 -1 -1
L 75600 61500 75400 61400 3 0 0 0 -1 -1
L 75400 61400 75600 61300 3 0 0 0 -1 -1
L 75600 61300 75400 61200 3 0 0 0 -1 -1
L 75400 61600 75600 61700 3 0 0 0 -1 -1
L 75600 61700 75500 61750 3 0 0 0 -1 -1
P 75500 61900 75500 61750 1 0 0
{
T 75450 61800 5 8 0 1 90 0 1
pinnumber=2
T 75450 61800 5 8 0 0 90 0 1
pinseq=2
}
P 75500 61000 75500 61152 1 0 0
{
T 75450 61100 5 8 0 1 90 0 1
pinnumber=1
T 75450 61100 5 8 0 0 90 0 1
pinseq=1
}
L 75400 61201 75500 61150 3 0 0 0 -1 -1
T 75200 61300 5 10 0 0 90 0 1
device=RESISTOR
T 75600 61000 8 10 0 1 90 0 1
pins=2
T 75600 61000 8 10 0 1 90 0 1
class=DISCRETE
]
{
T 75300 61400 5 10 1 1 180 0 1
refdes=R2
T 75600 61000 5 10 0 0 0 0 1
footprint=0805
}
N 75500 61000 75500 60800 4
N 75500 60800 74800 60800 4
{
T 74800 60800 5 10 1 1 0 0 1
netname=PGND
}
C 76800 61000 1 90 0 EMBEDDEDresistor.sym
[
L 76600 61600 76800 61500 3 0 0 0 -1 -1
L 76800 61500 76600 61400 3 0 0 0 -1 -1
L 76600 61400 76800 61300 3 0 0 0 -1 -1
L 76800 61300 76600 61200 3 0 0 0 -1 -1
L 76600 61600 76800 61700 3 0 0 0 -1 -1
L 76800 61700 76700 61750 3 0 0 0 -1 -1
P 76700 61900 76700 61750 1 0 0
{
T 76650 61800 5 8 0 1 90 0 1
pinnumber=2
T 76650 61800 5 8 0 0 90 0 1
pinseq=2
}
P 76700 61000 76700 61152 1 0 0
{
T 76650 61100 5 8 0 1 90 0 1
pinnumber=1
T 76650 61100 5 8 0 0 90 0 1
pinseq=1
}
L 76600 61201 76700 61150 3 0 0 0 -1 -1
T 76400 61300 5 10 0 0 90 0 1
device=RESISTOR
T 76800 61000 8 10 0 1 90 0 1
pins=2
T 76800 61000 8 10 0 1 90 0 1
class=DISCRETE
]
{
T 76500 61400 5 10 1 1 180 0 1
refdes=R3
T 76800 61000 5 10 0 0 0 0 1
footprint=0805
}
N 76700 60800 76000 60800 4
{
T 76000 60800 5 10 1 1 0 0 1
netname=PGND
}
N 76700 60600 76000 60600 4
{
T 76000 60600 5 10 1 1 0 0 1
netname=GND
}
N 76700 60600 76700 61000 4
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