Re: gEDA-user: Soft and Hard symbols

[Stephan Boettcher <boettcher@xxxxxxxxxxxxxxxxxx>]

Peter Clifton <pcjc2@xxxxxxxxx> writes:

> On Fri, 2011-01-14 at 21:14 -0500, al davis wrote:
>> Reading a file is easy.  The hard part about the geda format, 
>> where use of libgeda may be advantageous, is establishing 
>> connectivity.
>
> A mix of libgeda, with gnetlist wading in and flattening things (perhaps
> unhelpfully). I want to see all connectivity code move into libgeda, and
> flattening be optional.
>
>>   I don't know where that is done, or if it is done 
>> in a form that would be useful here, or whether there exists the 
>> code to go the other way (generate a schematic given a netlist 
>> and rendering info) which is equally needed.
>
> Not done. Would be nice though - but I'd rate it of similar complexity
> to a board auto-router. (Not as rigidly constrained topologically, but
> to do well would require a decent auto-place, and a decent auto-router -
> even if the rules are different to that used with a PCB).

Why would anybody want such a schematic?

I see two semi-graphical ways to express a netlist in gschem format.

1. Each element uses the same generic symbol, with the proper attributes
attached, and net= attributes for connectivity.  Placed on some grid in
arbitrary order, optionally so that the attribute lists do not overlap
when viewed graphically.

2. When symbols are available for the elements, those can be placed on
some grid, and each pin gets a little net stub with netname= for
connectivity.

Last millenium, some cadence netlister move such schematics from
synthesized Verilog netlist, but I do not remember why they were needed
in the flow, certainly not for human inspection.  

A mixture between 1. and 2., in case there is some way to feed an
element to symbol map into the process, falling back to 1. for elements
without symbols.  But that use case is 

What are the use-cases?

Mix gschem schematics with synthesis output into gnetlist for ASIC or
simulation targets?

-- 
Stephan


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